Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints

D
DATE
1999
Design, Automation and Test in Europe (DATE '99)
Abstract - Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints

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	Similar Articles Articles by R. Schwencker Articles by J. Eckmueller Articles by H. Graeb Articles by K. Antreich

Design, Automation and Test in Europe (DATE '99)

Munich, Germany

March 09-March 12

ISBN: 0-7695-0078-1

	ASCII Text	x
	R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich, "Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints," Design, Automation and Test in Europe Conference and Exhibition, pp. 323, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761141, author = {R. Schwencker and J. Eckmueller and H. Graeb and K. Antreich}, title = {Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {323}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761141}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints SN - 1530-1591 SP EP A1 - R. Schwencker, A1 - J. Eckmueller, A1 - H. Graeb, A1 - K. Antreich, PY - 1999 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

R. Schwencker, Institute of Electronic Design Automation and Technical University of Munich

J. Eckmueller, Technical University of Munich

H. Graeb, Institute of Electronic Design Automation

K. Antreich, Institute of Electronic Design Automation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761141

In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural constraints during the automatic sizing prevents pathologically sized circuits and speeds up the automatic sizing. The sizing is done with a sensitivity-based, iterative trust region method.

Citation:

R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich, "Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints," date, pp.323, Design, Automation and Test in Europe (DATE '99), 1999

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