Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs

D
DATE
1999
Design, Automation and Test in Europe (DATE '99)
Abstract - Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs

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Design, Automation and Test in Europe (DATE '99)

Munich, Germany

March 09-March 12

ISBN: 0-7695-0078-1

	ASCII Text	x
	Meenakshi Kaul, Ranga Vemuri, "Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs," Design, Automation and Test in Europe Conference and Exhibition, pp. 202, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761123, author = {Meenakshi Kaul and Ranga Vemuri}, title = {Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {202}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761123}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs SN - 1530-1591 SP EP A1 - Meenakshi Kaul, A1 - Ranga Vemuri, PY - 1999 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Meenakshi Kaul, University of Cincinnati

Ranga Vemuri, University of Cincinnati

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761123

We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. We present an iterative search procedure that uses a core ILP (Integer Linear Programming) technique, to obtain constraint satisfying solutions. The search procedure explores different regions of the design space while accomplishing combined partitioning and design space exploration. A case study of the DCT (Discrete Cosine Transform) demonstrates the effectiveness of our approach.

Citation:

Meenakshi Kaul, Ranga Vemuri, "Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs," date, pp.202, Design, Automation and Test in Europe (DATE '99), 1999

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