Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks

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Design, Automation and Test in Europe (DATE '99)

Munich, Germany

March 09-March 12

ISBN: 0-7695-0078-1

	ASCII Text	x
	D. Nikolos, H. T. Vergos, Th. Haniotakis, Y. Tsiatouhas, "Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks," Design, Automation and Test in Europe Conference and Exhibition, pp. 112, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761105, author = {D. Nikolos and H. T. Vergos and Th. Haniotakis and Y. Tsiatouhas}, title = {Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {112}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks SN - 1530-1591 SP EP A1 - D. Nikolos, A1 - H. T. Vergos, A1 - Th. Haniotakis, A1 - Y. Tsiatouhas, PY - 1999 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

D. Nikolos, University of Patras and Computer Technology Institute

H. T. Vergos, University of Patras and Computer Technology Institute

Th. Haniotakis, ISD S.A

Y. Tsiatouhas, ISD S.A

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761105

In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the Integrated Circuit (IC) can be used for path delay fault testing of the IC. We show that the testing of the IC for path delay faults can be reduced to the testing of each block. Intellectual Property (IP) blocks are treated as black boxes. The number of the circuit paths that must be tested is almost equal to the sum of the paths that must be tested for each block.

Citation:

D. Nikolos, H. T. Vergos, Th. Haniotakis, Y. Tsiatouhas, "Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks," date, pp.112, Design, Automation and Test in Europe (DATE '99), 1999

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