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Design Automation and Test in Europe (DATE '98)
CMOS Combinational Circuit Sizing by Stage-wise Tapering
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
ASCII Text
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Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija, "CMOS Combinational Circuit Sizing by Stage-wise Tapering," Design, Automation and Test in Europe Conference and Exhibition, pp. 985, Design Automation and Test in Europe (DATE '98), 1998.
 
 
BibTex
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@article{ 10.1109/DATE.1998.656001,
author = {Satyamurthy Pullela and Rajendran Panda and Abhijit Dharchoudhury and Gopal Vija},
title = {CMOS Combinational Circuit Sizing by Stage-wise Tapering},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1998},
isbn = {0-8186-8359-7},
pages = {985},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.656001},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - CMOS Combinational Circuit Sizing by Stage-wise Tapering
SN - 0-8186-8359-7
SP
EP
A1 - Satyamurthy Pullela,
A1 - Rajendran Panda,
A1 - Abhijit Dharchoudhury,
A1 - Gopal Vija,
PY - 1998
KW - Transistor sizing
KW - tapering
KW - resynthesis
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Satyamurthy Pullela, Monterey Design Systems, San Jose, CA
Rajendran Panda, Motorola Inc., Austin, TX
Abhijit Dharchoudhury, Motorola Inc., Austin, TX
Gopal Vija, Motorola Inc., Austin, TX
We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain, and uses tapering constants based on the position of a stage in a circuit, and the position of a transistor in a stack.
Index Terms:
Transistor sizing, tapering, resynthesis
Citation:
Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija, "CMOS Combinational Circuit Sizing by Stage-wise Tapering," date, pp.985, Design Automation and Test in Europe (DATE '98), 1998
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