Design Automation and Test in Europe (DATE '98) Path Verification Using Boolean Satisfiability Paris, France February 23-February 26 ISBN: 0-8186-8359-7
The importance of identifying false paths in a combinational circuit cannot be overstated since they may mask the true delay. We present a fast algorithm based on boolean satisfiability for solving this problem. We also present extensions to this per-path approach to find the critical path of a circuit in a reasonable time.
Index Terms:
Static Timing Analysis, False Path Problem, Satisfiability, Dynamic Esperance
Citation:
Matthias Ringe, Thomas Lindenkreuz, Erich Barke, "Path Verification Using Boolean Satisfiability," date, pp.965, Design Automation and Test in Europe (DATE '98), 1998 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||