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Design Automation and Test in Europe (DATE '98)
Architectural Rule Checking for High-level Synthesis
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
ASCII Text
x 
 
Jie Gong, Chih-Tung Chen, Kayhan Kucukcakar, "Architectural Rule Checking for High-level Synthesis," Design, Automation and Test in Europe Conference and Exhibition, pp. 949, Design Automation and Test in Europe (DATE '98), 1998.
 
 
BibTex
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@article{ 10.1109/DATE.1998.655983,
author = {Jie Gong and Chih-Tung Chen and Kayhan Kucukcakar},
title = {Architectural Rule Checking for High-level Synthesis},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1998},
isbn = {0-8186-8359-7},
pages = {949},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655983},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Architectural Rule Checking for High-level Synthesis
SN - 0-8186-8359-7
SP
EP
A1 - Jie Gong,
A1 - Chih-Tung Chen,
A1 - Kayhan Kucukcakar,
PY - 1998
KW - Rule Checking
KW - High-level Synthesis
KW - Verification
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Jie Gong, Unified Design System Laboratory
Chih-Tung Chen, Unified Design System Laboratory
Kayhan Kucukcakar, Unified Design System Laboratory
Verifying an implementation produced from high-level synthesis is a challenging problem due to many complex design tasks involved in the design process. In this paper, we present an architectural rule checking approach for high-level design verification. This technique detects and locates various design errors and verifies both the consistency and correctness of an implementation. Besides describing different rule suites, we also report a working environment for the architectural rule checking. Finally, we highlight the value of the proposed approach with a real-life design.
Index Terms:
Rule Checking, High-level Synthesis, Verification
Citation:
Jie Gong, Chih-Tung Chen, Kayhan Kucukcakar, "Architectural Rule Checking for High-level Synthesis," date, pp.949, Design Automation and Test in Europe (DATE '98), 1998
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