A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design

D
DATE
1998
Design Automation and Test in Europe (DATE '98)
Abstract - A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design

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Design Automation and Test in Europe (DATE '98)

Paris, France

February 23-February 26

ISBN: 0-8186-8359-7

	ASCII Text	x
	J. A. Montiel-Nelson, V. de Armas, R. Sarmiento, A. Nunez, "A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design," Design, Automation and Test in Europe Conference and Exhibition, pp. 947, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655982, author = {J. A. Montiel-Nelson and V. de Armas and R. Sarmiento and A. Nunez}, title = {A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {947}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655982}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design SN - 0-8186-8359-7 SP EP A1 - J. A. Montiel-Nelson, A1 - V. de Armas, A1 - R. Sarmiento, A1 - A. Nunez, PY - 1998 KW - Gallium Arsenide automated layout generation system KW - GaAs VLSI design KW - power supply and ground distribution model KW - full-custom cell layout style KW - full-custom layouts of very high speed circuits KW - cell library builder KW - random logic macrocell generator KW - iterative logic array generator. VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

J. A. Montiel-Nelson, University of Las Palmas de Gran Canaria

V. de Armas, University of Las Palmas de Gran Canaria

R. Sarmiento, University of Las Palmas de Gran Canaria

A. Nunez, University of Las Palmas de Gran Canaria

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655982

A Gallium Arsenide automated layout generation system (OLYMPO) for SSI, MSI and LSI circuits used in GaAs VLSI design has been developed. We introduce a full-custom layout style, called RN-based cell model, that it is suited to generate low self-inductance circuit layouts of cells and macrocells. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. Experimental results demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.

Index Terms:

Gallium Arsenide automated layout generation system, GaAs VLSI design, power supply and ground distribution model, full-custom cell layout style, full-custom layouts of very high speed circuits, cell library builder, random logic macrocell generator, iterative logic array generator.

Citation:

J. A. Montiel-Nelson, V. de Armas, R. Sarmiento, A. Nunez, "A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design," date, pp.947, Design Automation and Test in Europe (DATE '98), 1998

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