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Design Automation and Test in Europe (DATE '98)
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
M.L. Flottes, Micro?lectronique de Montpellier,U.M. CNRS 9928
R. Pires, Micro?lectronique de Montpellier,U.M. CNRS 9928
B. Rouzeyre, Micro?lectronique de Montpellier,U.M. CNRS 9928
L. Volpe, Micro?lectronique de Montpellier,U.M. CNRS 9928
In this paper, we present a method for quickly identifying the scan path chain of datapaths. The originality of the method resides in working with both RT and gate-level level descriptions of circuits. The proposed technique results in a very significant reduction on the CPU time required for scan path selection. We investigate also some directions for the incorporation of partial scan methodology within High Level Synthesis for Testability.
Index Terms:
Partial scan, Scan chain selection, Synthesis for testability, RT and gate levels
Citation:
M.L. Flottes, R. Pires, B. Rouzeyre, L. Volpe, "Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique," date, pp.921, Design Automation and Test in Europe (DATE '98), 1998
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