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Design Automation and Test in Europe (DATE '98)
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
ASCII Text
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J. A. Prieto, A. Rueda, I. Grout, E. Peralías, J. L. Huertas, A. M. D. Richardson, "An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits," Design, Automation and Test in Europe Conference and Exhibition, pp. 905, Design Automation and Test in Europe (DATE '98), 1998.
 
 
BibTex
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@article{ 10.1109/DATE.1998.655965,
author = {J. A. Prieto and A. Rueda and I. Grout and E. Peralías and J. L. Huertas and A. M. D. Richardson},
title = {An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1998},
isbn = {0-8186-8359-7},
pages = {905},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655965},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits
SN - 0-8186-8359-7
SP
EP
A1 - J. A. Prieto,
A1 - A. Rueda,
A1 - I. Grout,
A1 - E. Peralías,
A1 - J. L. Huertas,
A1 - A. M. D. Richardson,
PY - 1998
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.
Citation:
J. A. Prieto, A. Rueda, I. Grout, E. Peralías, J. L. Huertas, A. M. D. Richardson, "An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits," date, pp.905, Design Automation and Test in Europe (DATE '98), 1998
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