Instruction Scheduling for Power Reduction in Processor-Based System Design

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Design Automation and Test in Europe (DATE '98)

Paris, France

February 23-February 26

ISBN: 0-8186-8359-7

	ASCII Text	x
	Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura, "Instruction Scheduling for Power Reduction in Processor-Based System Design," Design, Automation and Test in Europe Conference and Exhibition, pp. 855, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655958, author = {Hiroyuki Tomiyama and Tohru Ishihara and Akihiko Inoue and Hiroto Yasuura}, title = {Instruction Scheduling for Power Reduction in Processor-Based System Design}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {855}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655958}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Instruction Scheduling for Power Reduction in Processor-Based System Design SN - 0-8186-8359-7 SP EP A1 - Hiroyuki Tomiyama, A1 - Tohru Ishihara, A1 - Akihiko Inoue, A1 - Hiroto Yasuura, PY - 1998 KW - Low-Power Design KW - Instruction Scheduling KW - Caches VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Hiroyuki Tomiyama, Kyushu University

Tohru Ishihara, Kyushu University

Akihiko Inoue, Kyushu University

Hiroto Yasuura, Kyushu University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655958

This paper propose an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.

Index Terms:

Low-Power Design, Instruction Scheduling, Caches

Citation:

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura, "Instruction Scheduling for Power Reduction in Processor-Based System Design," date, pp.855, Design Automation and Test in Europe (DATE '98), 1998

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