Efficient Minarea Retiming of Large Level-Clocked Circuits

D
DATE
1998
Design Automation and Test in Europe (DATE '98)
Abstract - Efficient Minarea Retiming of Large Level-Clocked Circuits

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	Similar Articles Articles by Naresh Maheshwari Articles by Sachin S. Sapatnekar

Design Automation and Test in Europe (DATE '98)

Paris, France

February 23-February 26

ISBN: 0-8186-8359-7

	ASCII Text	x
	Naresh Maheshwari, Sachin S. Sapatnekar, "Efficient Minarea Retiming of Large Level-Clocked Circuits," Design, Automation and Test in Europe Conference and Exhibition, pp. 840, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655956, author = {Naresh Maheshwari and Sachin S. Sapatnekar}, title = {Efficient Minarea Retiming of Large Level-Clocked Circuits}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {840}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655956}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Efficient Minarea Retiming of Large Level-Clocked Circuits SN - 0-8186-8359-7 SP EP A1 - Naresh Maheshwari, A1 - Sachin S. Sapatnekar, PY - 1998 KW - Optimization KW - Level-clocked KW - Retiming KW - Area KW - Synthesis VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Naresh Maheshwari, Iowa State University, Ames IA

Sachin S. Sapatnekar, University of Minnesota, Minneapolis, MN

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655956

Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).

Index Terms:

Optimization, Level-clocked, Retiming, Area, Synthesis

Citation:

Naresh Maheshwari, Sachin S. Sapatnekar, "Efficient Minarea Retiming of Large Level-Clocked Circuits," date, pp.840, Design Automation and Test in Europe (DATE '98), 1998

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