Switching Response Modeling of the CMOS Inverter for Sub-micron Devices

D
DATE
1998
Design Automation and Test in Europe (DATE '98)
Abstract - Switching Response Modeling of the CMOS Inverter for Sub-micron Devices

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Design Automation and Test in Europe (DATE '98)

Paris, France

February 23-February 26

ISBN: 0-8186-8359-7

	ASCII Text	x
	L. Bisdounis, O. Koufopavlou, C. Goutis, S. Nikolaidis, "Switching Response Modeling of the CMOS Inverter for Sub-micron Devices," Design, Automation and Test in Europe Conference and Exhibition, pp. 729, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655939, author = {L. Bisdounis and O. Koufopavlou and C. Goutis and S. Nikolaidis}, title = {Switching Response Modeling of the CMOS Inverter for Sub-micron Devices}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {729}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655939}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Switching Response Modeling of the CMOS Inverter for Sub-micron Devices SN - 0-8186-8359-7 SP EP A1 - L. Bisdounis, A1 - O. Koufopavlou, A1 - C. Goutis, A1 - S. Nikolaidis, PY - 1998 KW - CMOS circuits timing analysis KW - Propagation delay modeling KW - Sub-micron devices. VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

L. Bisdounis, University of Patras

O. Koufopavlou, University of Patras

C. Goutis, University of Patras

S. Nikolaidis, Aristotle University of Thessaloniki

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655939

In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub- micron regime, is presented. A detailed analysis of the inverter operation is provided which results to accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short- circuit current during switching, and the gate-to- drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.

Index Terms:

CMOS circuits timing analysis, Propagation delay modeling, Sub-micron devices.

Citation:

L. Bisdounis, O. Koufopavlou, C. Goutis, S. Nikolaidis, "Switching Response Modeling of the CMOS Inverter for Sub-micron Devices," date, pp.729, Design Automation and Test in Europe (DATE '98), 1998

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