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Design Automation and Test in Europe (DATE '98)
Sequential Equivalence Checking without State Space Traversal
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
C.A.J. Van Eijk, Eindhoven University of Technology
Because general algorithms for sequential equivalence checking require a state space traversal of the product machine, they are computationally expensive. In this paper, we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the state space traversal. The effectiveness of the proposed method is confirmed by experimental results on retimed and optimized ISCAS'89 benchmarks.
Citation:
C.A.J. Van Eijk, "Sequential Equivalence Checking without State Space Traversal," date, pp.618, Design Automation and Test in Europe (DATE '98), 1998
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