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Design Automation and Test in Europe (DATE '98)
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures
Paris, France
February 23-February 26
ISBN: 0-8186-8359-7
ASCII Text
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Meenakshi Kaul, Ranga Vemuri, "Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures," Design, Automation and Test in Europe Conference and Exhibition, pp. 389, Design Automation and Test in Europe (DATE '98), 1998.
 
 
BibTex
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@article{ 10.1109/DATE.1998.655887,
author = {Meenakshi Kaul and Ranga Vemuri},
title = {Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1998},
isbn = {0-8186-8359-7},
pages = {389},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655887},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures
SN - 0-8186-8359-7
SP
EP
A1 - Meenakshi Kaul,
A1 - Ranga Vemuri,
PY - 1998
KW - Temporal Partitioning
KW - Synthesis
KW - Non-linear programming
KW - Integer Linear programming
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Meenakshi Kaul, University of Cincinnati
Ranga Vemuri, University of Cincinnati
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and high-level synthesis from behavioral specifications destined to be implemented on reconfigurable processors. We present tight linearizations of the NLP model. We present effective variable selection heuristics for a branch and bound solution of the derived linear programming model. We show how tight linearizations combined with good variable selection techniques during branch and bound yield optimal results in relatively short execution times.
Index Terms:
Temporal Partitioning, Synthesis, Non-linear programming, Integer Linear programming
Citation:
Meenakshi Kaul, Ranga Vemuri, "Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures," date, pp.389, Design Automation and Test in Europe (DATE '98), 1998
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