Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset

D
DATE
1998
Design Automation and Test in Europe (DATE '98)
Abstract - Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset

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	Similar Articles Articles by Uwe Fassnacht Articles by Juergen Schietke

Design Automation and Test in Europe (DATE '98)

Paris, France

February 23-February 26

ISBN: 0-8186-8359-7

	ASCII Text	x
	Uwe Fassnacht, Juergen Schietke, "Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset," Design, Automation and Test in Europe Conference and Exhibition, pp. 325, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655876, author = {Uwe Fassnacht and Juergen Schietke}, title = {Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {325}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655876}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset SN - 0-8186-8359-7 SP EP A1 - Uwe Fassnacht, A1 - Juergen Schietke, PY - 1998 KW - Timing KW - timing optimization KW - static timing analysis VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Uwe Fassnacht, IBM Entwicklung GmbH Boeblingen

Juergen Schietke, University of Bonn

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655876

We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server - Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization schemes and present obtained results.

Index Terms:

Timing, timing optimization, static timing analysis

Citation:

Uwe Fassnacht, Juergen Schietke, "Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset," date, pp.325, Design Automation and Test in Europe (DATE '98), 1998

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