This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing an architecture to implement the lossless compression of medical images using DWT. The datapath word-length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The architecture has been simulated in VHDL and has a hardware utilization efficiency greater than 99%. It can compute the FDWT/IDWT at a rate of 3.5 512'512 12 bit images/s corresponding to a clock speed of 33MHz.