Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

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	Similar Articles Articles by Petru Eles Articles by Krzysztof Kuchcinski Articles by Zebo Peng Articles by Alexa Doboli Articles by Paul Pop

Design Automation and Test in Europe (DATE '98)

Paris, France

February 23-February 26

ISBN: 0-8186-8359-7

	ASCII Text	x
	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop, "Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems," Design, Automation and Test in Europe Conference and Exhibition, pp. 132, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655847, author = {Petru Eles and Krzysztof Kuchcinski and Zebo Peng and Alexa Doboli and Paul Pop}, title = {Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {132}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655847}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems SN - 0-8186-8359-7 SP EP A1 - Petru Eles, A1 - Krzysztof Kuchcinski, A1 - Zebo Peng, A1 - Alexa Doboli, A1 - Paul Pop, PY - 1998 KW - Embedded systems KW - Hardware/Software co-design KW - Process scheduling KW - System design KW - Design automation KW - System-level synthesis KW - Real time systems KW - Performance estimation VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655847

We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Index Terms:

Embedded systems, Hardware/Software co-design, Process scheduling, System design, Design automation, System-level synthesis, Real time systems, Performance estimation

Citation:

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop, "Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems," date, pp.132, Design Automation and Test in Europe (DATE '98), 1998

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