Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing

A
ATS
2004
13th Asian Test Symposium (ATS'04)
Abstract - Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing

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13th Asian Test Symposium (ATS'04)

Kenting, Taiwan

November 15-November 17

ISBN: 0-7695-2235-1

	ASCII Text	x
	Ho Fai Ko, Nicola Nicolici, "Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing," Asian Test Symposium, pp. 454-459, 13th Asian Test Symposium (ATS'04), 2004.

	BibTex	x
	@article{ 10.1109/ATS.2004.47, author = {Ho Fai Ko and Nicola Nicolici}, title = {Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing}, journal ={Asian Test Symposium}, volume = {0}, year = {2004}, issn = {1081-7735}, pages = {454-459}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2004.47}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing SN - 1081-7735 SP454 EP459 A1 - Ho Fai Ko, A1 - Nicola Nicolici, PY - 2004 KW - High-level DFT KW - Delay-fault testing VL - 0 JA - Asian Test Symposium ER -

Ho Fai Ko, McMaster University

Nicola Nicolici, McMaster University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.47

This paper introduces a new method to construct functional scan chains at the register-transfer level aimed at increasing the delay fault coverage when using the skewed-load test application strategy. It is shown how by consciously creating scan paths prior to logic synthesis, both the transition delay fault coverage and circuit speed can be improved.

Index Terms:

High-level DFT, Delay-fault testing

Citation:

Ho Fai Ko, Nicola Nicolici, "Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing," ats, pp.454-459, 13th Asian Test Symposium (ATS'04), 2004

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