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13th Asian Test Symposium (ATS'04)
Burn-In Stress Test of Analog CMOS ICs
Kenting, Taiwan
November 15-November 17
ISBN: 0-7695-2235-1
ASCII Text
x 
 
Chin-Long Wey, Meng-Yao Liu, "Burn-In Stress Test of Analog CMOS ICs," Asian Test Symposium, pp. 360-365, 13th Asian Test Symposium (ATS'04), 2004.
 
 
BibTex
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@article{ 10.1109/ATS.2004.28,
author = {Chin-Long Wey and Meng-Yao Liu},
title = {Burn-In Stress Test of Analog CMOS ICs},
journal ={Asian Test Symposium},
volume = {0},
year = {2004},
issn = {1081-7735},
pages = {360-365},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2004.28},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Burn-In Stress Test of Analog CMOS ICs
SN - 1081-7735
SP360
EP365
A1 - Chin-Long Wey,
A1 - Meng-Yao Liu,
PY - 2004
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
Chin-Long Wey, National Central University
Meng-Yao Liu, National Central University
With the successful development of EVoSTA (Extreme-Voltage Stress Test for Analog CMOS ICs), this paper investigated whether the extreme-temperature Burn-in stress test is properly applied for enhancing the gate-oxide reliability of mixed-signal/analog CMOS ICs. Burn-in is an effective screening method used in predicting, achieving, and enhancing field reliability of ICs. Today, almost all IC manufacturers perform 100% burn-in for various durations to screen defective products. However, the major problems associated with burn-in are the determination of exactly how long the burn-in process should continue, balancing appropriately the needs of reliability and the total costs, and what stress vectors should be applied? This paper conducted a feasibility study for resolving such issues.
Citation:
Chin-Long Wey, Meng-Yao Liu, "Burn-In Stress Test of Analog CMOS ICs," ats, pp.360-365, 13th Asian Test Symposium (ATS'04), 2004
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