Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores

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13th Asian Test Symposium (ATS'04)

Kenting, Taiwan

November 15-November 17

ISBN: 0-7695-2235-1

	ASCII Text	x
	Sukanta Das, Biplab K. Sikdar, P Pal Chaudhuri, "Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores," Asian Test Symposium, pp. 331-334, 13th Asian Test Symposium (ATS'04), 2004.

	BibTex	x
	@article{ 10.1109/ATS.2004.63, author = {Sukanta Das and Biplab K. Sikdar and P Pal Chaudhuri}, title = {Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores}, journal ={Asian Test Symposium}, volume = {0}, year = {2004}, issn = {1081-7735}, pages = {331-334}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2004.63}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores SN - 1081-7735 SP331 EP334 A1 - Sukanta Das, A1 - Biplab K. Sikdar, A1 - P Pal Chaudhuri, PY - 2004 KW - null VL - 0 JA - Asian Test Symposium ER -

Sukanta Das, Bengal Engineering College

Biplab K. Sikdar, Bengal Engineering College

P Pal Chaudhuri, Flat E4

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.63

This paper reports an efficient design of Test Pattern Generators (TPGs) for a chip having multiple cores. It is built around nonlinear Cellular Automata (CA) based Pseudo-Random Pattern Generator (PRPG). The modular and cascadable structure of proposed n-cell PRPG can be utilized to construct the (n = 1)-cell PRPG without sacrificing the pseudo-randomness quality. The efficiency of such a scalable PRPG structure is demonstrated in designing the on-chip TPGs for a VLSI chip implementing multiple cores.

Citation:

Sukanta Das, Biplab K. Sikdar, P Pal Chaudhuri, "Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores," ats, pp.331-334, 13th Asian Test Symposium (ATS'04), 2004

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