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13th Asian Test Symposium (ATS'04)
A Novel Approach for On-line Testable Reversible Logic Circuit Design
Kenting, Taiwan
November 15-November 17
ISBN: 0-7695-2235-1
ASCII Text
x 
 
D. P. Vasudevan, P. K. Lala, J. P. Parkerson, "A Novel Approach for On-line Testable Reversible Logic Circuit Design," Asian Test Symposium, pp. 325-330, 13th Asian Test Symposium (ATS'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/ATS.2004.13,
author = {D. P. Vasudevan and P. K. Lala and J. P. Parkerson},
title = {A Novel Approach for On-line Testable Reversible Logic Circuit Design},
journal ={Asian Test Symposium},
volume = {0},
year = {2004},
issn = {1081-7735},
pages = {325-330},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2004.13},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - A Novel Approach for On-line Testable Reversible Logic Circuit Design
SN - 1081-7735
SP325
EP330
A1 - D. P. Vasudevan,
A1 - P. K. Lala,
A1 - J. P. Parkerson,
PY - 2004
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
D. P. Vasudevan, University of Arkansas
P. K. Lala, University of Arkansas
J. P. Parkerson, University of Arkansas
Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.
Citation:
D. P. Vasudevan, P. K. Lala, J. P. Parkerson, "A Novel Approach for On-line Testable Reversible Logic Circuit Design," ats, pp.325-330, 13th Asian Test Symposium (ATS'04), 2004
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