loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
13th Asian Test Symposium (ATS'04)
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores
Kenting, Taiwan
November 15-November 17
ISBN: 0-7695-2235-1
Kazuko Kambe, Nara Institute of Science and Technology
Michiko Inoue, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
This paper presents a method of template generation for instruction-based self test of processor cores. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and propagation of test responses for a module under test (MUT). In order to justify value of MUT inputs, we introduce a concept of adjacent registers of the MUT that makes it possible to consider input spaces of the MUT determined by signals from other modules as well as signals directly from registers. We efficiently generate possible templates considering dependence of instructions each of which invokes one or more data transfers between registers. The method also generates multiple templates in effective order to detect faults, which may cover different input spaces, and therefore, different detectable fault sets.
Citation:
Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, "Efficient Template Generation for Instruction-Based Self-Test of Processor Cores," ats, pp.152-157, 13th Asian Test Symposium (ATS'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.