A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC

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13th Asian Test Symposium (ATS'04)

Kenting, Taiwan

November 15-November 17

ISBN: 0-7695-2235-1

	ASCII Text	x
	Guan-Xun Chen, Chung-Len Lee, Jwu-E Chen, "A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC," Asian Test Symposium, pp. 58-61, 13th Asian Test Symposium (ATS'04), 2004.

	BibTex	x
	@article{ 10.1109/ATS.2004.10, author = {Guan-Xun Chen and Chung-Len Lee and Jwu-E Chen}, title = {A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC}, journal ={Asian Test Symposium}, volume = {0}, year = {2004}, issn = {1081-7735}, pages = {58-61}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2004.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC SN - 1081-7735 SP58 EP61 A1 - Guan-Xun Chen, A1 - Chung-Len Lee, A1 - Jwu-E Chen, PY - 2004 KW - null VL - 0 JA - Asian Test Symposium ER -

Guan-Xun Chen, National Chiao Tung University

Chung-Len Lee, National Chiao Tung University

Jwu-E Chen, National Chung Hua University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.10

In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.

Citation:

Guan-Xun Chen, Chung-Len Lee, Jwu-E Chen, "A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC," ats, pp.58-61, 13th Asian Test Symposium (ATS'04), 2004

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