This paper introduces a new I_DDT test generation method based on the fact that a gate delay may differ from its nominal value. The Bayesian optimization algorithm based on genetic algorithm is utilized for I_DDT test generation. The paper proposals a fitness function to evaluate the evolutions of the test patterns and use a pseudo-probability method to create the first generation test patterns. The test patterns generated by the new approach are proved to be valid by the waveform simulator based on Boolean Process, even though gate delays are assigned randomly from 50% to 150% of their nominal values, and the number of the evolution generation can be reduced about 25%.