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12th Asian Test Symposium (ATS'03)
A BIST Circuit for IDDQ Tests
Xi?an, China
November 16-November 19
ISBN: 0-7695-1951-2
ASCII Text
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Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita, "A BIST Circuit for I<sub>DDQ</sub> Tests," Asian Test Symposium, pp. 390, 12th Asian Test Symposium (ATS'03), 2003.
 
 
BibTex
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@article{ 10.1109/ATS.2003.1250843,
author = {Masaki Hashizume and Teppei Takeda and Hiroyuki Yotsuyanagi and Takeomi Tamesada and Yukiya Miura and Kozo Kinoshita},
title = {A BIST Circuit for I<sub>DDQ</sub> Tests},
journal ={Asian Test Symposium},
volume = {0},
year = {2003},
issn = {1081-7735},
pages = {390},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250843},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - A BIST Circuit for I<sub>DDQ</sub> Tests
SN - 1081-7735
SP
EP
A1 - Masaki Hashizume,
A1 - Teppei Takeda,
A1 - Hiroyuki Yotsuyanagi,
A1 - Takeomi Tamesada,
A1 - Yukiya Miura,
A1 - Kozo Kinoshita,
PY - 2003
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
Masaki Hashizume, University of Tokushima
Teppei Takeda, University of Tokushima
Hiroyuki Yotsuyanagi, University of Tokushima
Takeomi Tamesada, University of Tokushima
Yukiya Miura, Tokyo Metropolitan University
Kozo Kinoshita, Osaka Gakuin University
An IDDQ test time reduction method is proposed which is suitable for BIST approaches in this paper. Also, a BIST circuit for IDDQ tests based on the method is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performances are evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using the test circuit.
Citation:
Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita, "A BIST Circuit for IDDQ Tests," ats, pp.390, 12th Asian Test Symposium (ATS'03), 2003
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