In this paper we are presenting a test methodology for performing module-based mixed level fault simulation and test generation on System-on-Chip (SOC) combinational Intellectual Property (IP) cores for which both a pre-synthesis behavioral description and a post-synthesis netlist is available but in an analyzer output intermediate format not readable by core integraters. We use the Verilog Procedural Interface (VPI) to access and perform serial fault simulation on a pre-compiled core available as a mixed behavioral-structural level design. We also use VPI to prepare a testbench environment for performing random pattern test generation. The simulation time results of applying this VPI-based test methodology on ISCAS85 Verilog benchmarks are also presented and compared to the flat (non-mixed level) version the proposed VPI-based environment.