Custom VLSI design at the switch level is commonly needed when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models for custom logic are created manually from the switch level models — a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. Besides providing comparable test quality, the test model created by automated flow maintains structural similarity to the original switch-level circuit which facilitates failure analysis greatly. The automated flow has been in use for the past several years within Motorola for the high performance processor family implementing the PowerPC instruction set architecture. We present experimental results on MPC7455.