Most of the recently discussed test stimulus data compression techniques are based on the low care bit densities found in typical scan test vectors. Data reduction primarily is achieved by compressing the don?t-care bit information, while maintaining the care bit data. The original care bit density, hence, dominates the theoretical compression limits.

This paper discusses potential on-chip hardware decoder architectures that allow for combining care bit oriented methods with test cube clustering to achieve multi-level test stimulus compression that reduces the data for both care bits and don?t-care bits.