PLL Based High Speed Functional Testing

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12th Asian Test Symposium (ATS'03)

Xi?an, China

November 16-November 19

ISBN: 0-7695-1951-2

	ASCII Text	x
	Jayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. Iyer, Andrew A.O. Tay, "PLL Based High Speed Functional Testing," Asian Test Symposium, pp. 116, 12th Asian Test Symposium (ATS'03), 2003.

	BibTex	x
	@article{ 10.1109/ATS.2003.1250794, author = {Jayasanker Jayabalan and Chee Kiang Goh and Ooi Ban Leong and Leong Mook Seng and Mahadevan K. Iyer and Andrew A.O. Tay}, title = {PLL Based High Speed Functional Testing}, journal ={Asian Test Symposium}, volume = {0}, year = {2003}, issn = {1081-7735}, pages = {116}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250794}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - PLL Based High Speed Functional Testing SN - 1081-7735 SP EP A1 - Jayasanker Jayabalan, A1 - Chee Kiang Goh, A1 - Ooi Ban Leong, A1 - Leong Mook Seng, A1 - Mahadevan K. Iyer, A1 - Andrew A.O. Tay, PY - 2003 KW - null VL - 0 JA - Asian Test Symposium ER -

Jayasanker Jayabalan, National University of Singapore

Chee Kiang Goh, Infineon Technologies

Ooi Ban Leong, National University of Singapore

Leong Mook Seng, National University of Singapore

Mahadevan K. Iyer, Institute of Microelectronics

Andrew A.O. Tay, National University of Singapore

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250794

A PLL based at-speed functional testing concept, which eliminates the need for a tester-driven high-speed clock interface is presented. Jitter tolerance circuits have been implemented to provide immunity to clock jitter. The concept was verified on a 100 square mm silicon device built in 0.18 micron technology above 200 MHz speed. Simulation results show that the concept can be extended to higher speeds.

Citation:

Jayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. Iyer, Andrew A.O. Tay, "PLL Based High Speed Functional Testing," ats, pp.116, 12th Asian Test Symposium (ATS'03), 2003

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