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12th Asian Test Symposium (ATS'03)
On Estimation of Fault Efficiency for Path Delay Faults
Xi?an, China
November 16-November 19
ISBN: 0-7695-1951-2
Masayasu Fukunaga, Kyushu Institute of Technology
Seiji Kajihara, Kyushu Institute of Technology
Sadami Takeoka, Matsushita Electric Industrial Co., Ltd. Semiconductor Company
In this paper, we propose a method to estimate fault efficiency for path delay faults based on untestable path analysis. In path delay fault testing, fault coverage of test patterns is usually very low, because logic circuits often have huge number of paths including many untestable paths. Hence we should compute fault efficiency rather than fault coverage, but it is too difficult to compute exact fault efficiency in a short time, because there is no method to compute total number of untestable paths quickly. The proposed method statistically estimate the number of untestable paths based on untestable path analysis, and compute fault efficiency. Experimental results show that the proposed method can accurately estimate fault efficiency of given test patterns in a reasonable time.
Citation:
Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, "On Estimation of Fault Efficiency for Path Delay Faults," ats, pp.64, 12th Asian Test Symposium (ATS'03), 2003
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