When VLSI design and process enter the stage of ultra deep submicron (UDSM), process variations, signal integrity (SI) and design integrity (DI) issues can no longer be ignored. These factors introduce some new problems in VLSI design, test and diagnosis, which increase time-to-market, time-to-volume and cost for silicon debug. Intermittent scan chain hold-time fault is one of such problems we encountered in practice. The fault sites have to be located to speedup silicon debug and improve yield.

Recent study of the problem proposed a statistical algorithm to diagnose the faulty scan chains if only one fault per chain. Based on the previous work, in this paper, an efficient diagnosis algorithm is proposed to diagnose faulty scan chains with multiple faults per chain. The presented experimental results on industrial designs show that the proposed algorithm achieves good diagnosis resolution in reasonable time.