Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces

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	Similar Articles Articles by Zaid Al-Ars Articles by Ad J. van de Goor

12th Asian Test Symposium (ATS'03)

Xi?an, China

November 16-November 19

ISBN: 0-7695-1951-2

	ASCII Text	x
	Zaid Al-Ars, Ad J. van de Goor, "Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces," Asian Test Symposium, pp. 24, 12th Asian Test Symposium (ATS'03), 2003.

	BibTex	x
	@article{ 10.1109/ATS.2003.1250777, author = {Zaid Al-Ars and Ad J. van de Goor}, title = {Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces}, journal ={Asian Test Symposium}, volume = {0}, year = {2003}, issn = {1081-7735}, pages = {24}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250777}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces SN - 1081-7735 SP EP A1 - Zaid Al-Ars, A1 - Ad J. van de Goor, PY - 2003 KW - DRAMs KW - process variations KW - border resistance trace KW - defect simulation KW - memory testing VL - 0 JA - Asian Test Symposium ER -

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250777

As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memories. This paper discusses the issue of process variations, and shows how to deal with it in the context of fault analysis and test generation. The paper also introduces the concept of border resistance traces as a tool to optimize test stresses and inspect the impact of process variations on the optimization procedure. The concepts are discussed in the paper with the help of a practical example of a specific defect in the memory.

Index Terms:

DRAMs, process variations, border resistance trace, defect simulation, memory testing

Citation:

Zaid Al-Ars, Ad J. van de Goor, "Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces," ats, pp.24, 12th Asian Test Symposium (ATS'03), 2003

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