In this paper, a new method for reducing scan shift is presented. Scan design is one of the most popular design for test technology for sequential circuits. However, it requires much test application time and test data when applied for circuits with many .ip-.ops. The new scan method utilizes two con.guration of scan chains, a folding scan tree and a fully compatible scan tree. Using test pattern including many don?t care values are used to con.gure a fully compatible scan tree in order to reduce scan shift without degrading fault coverage. And then a folding scan tree is configured to reduce the length of scan chain to reduce scan shift. Experimental results for benchmark circuits shows this scan method can reduce many scan shifts.