The rapid growing trend of utilization of reuseable Intellectual Property (IP) cores for System-On-Chip (SOC) design demanding an effective, fast and efficient test scheme. This paper presents an unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores? test output voltages (SOCTOV) which has the advantages of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sum of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to the SOC testing especially when chip area overhead is a critical concern.