For recent VLSIs designe for low power, reduction of power dissipation during test is one of the most impor- tant problems. This paper presents a metho to reduce power dissipation during test for sequential circuits. The goal is to obtain test vectors for sequential circuits that achieve low power dissipation. In our method,test vectors generate by ATPG are given and they are im- prove to reduce power dissipation without losing the original stuck-at fault coverage. Due to the correlation between power dissipation and the number of transition gates, the number of transition gates is evaluate for each test vector during modification of test vectors. In order to keep the original fault coverage, logic simula- tion and fault simulation are performed, every time a test vector is modified. The effectiveness of our method is shown by experimental results for ISCAS ?89 bench- mark circuits.