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11th Asian Test Symposium (ATS'02)
Manufacturing Test of SoCs
Guam, USA
November 18-November 20
ISBN: 0-7695-1825-7
ASCII Text
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Rohit Kapur, T.W. Williams, "Manufacturing Test of SoCs," Asian Test Symposium, pp. 317, 11th Asian Test Symposium (ATS'02), 2002.
 
 
BibTex
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@article{ 10.1109/ATS.2002.1181730,
author = {Rohit Kapur and T.W. Williams},
title = {Manufacturing Test of SoCs},
journal ={Asian Test Symposium},
volume = {0},
year = {2002},
issn = {1081-7735},
pages = {317},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181730},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asian Test Symposium
TI - Manufacturing Test of SoCs
SN - 1081-7735
SP
EP
A1 - Rohit Kapur,
A1 - T.W. Williams,
PY - 2002
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
Rohit Kapur, Synopsys Inc.
T.W. Williams, Synopsys Inc.
In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.
Citation:
Rohit Kapur, T.W. Williams, "Manufacturing Test of SoCs," ats, pp.317, 11th Asian Test Symposium (ATS'02), 2002
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