A SoC Test Strategy Based on a Non-Scan DFT Method

A
ATS
2002
11th Asian Test Symposium (ATS'02)
Abstract - A SoC Test Strategy Based on a Non-Scan DFT Method

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11th Asian Test Symposium (ATS'02)

Guam, USA

November 18-November 20

ISBN: 0-7695-1825-7

	ASCII Text	x
	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka, "A SoC Test Strategy Based on a Non-Scan DFT Method," Asian Test Symposium, pp. 305, 11th Asian Test Symposium (ATS'02), 2002.

	BibTex	x
	@article{ 10.1109/ATS.2002.1181728, author = {Hiroshi Date and Toshinori Hosokawa and Michiaki Muraoka}, title = {A SoC Test Strategy Based on a Non-Scan DFT Method}, journal ={Asian Test Symposium}, volume = {0}, year = {2002}, issn = {1081-7735}, pages = {305}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181728}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A SoC Test Strategy Based on a Non-Scan DFT Method SN - 1081-7735 SP EP A1 - Hiroshi Date, A1 - Toshinori Hosokawa, A1 - Michiaki Muraoka, PY - 2002 KW - null VL - 0 JA - Asian Test Symposium ER -

Hiroshi Date, Semiconductor Technology Academic Research Center (STARC)

Toshinori Hosokawa, Semiconductor Technology Academic Research Center (STARC)

Michiaki Muraoka, Semiconductor Technology Academic Research Center (STARC)

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181728

This paper proposes a System-on-a-Chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.

Keywords : SoC test, non-scan DFT, high level design and test

Citation:

Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka, "A SoC Test Strategy Based on a Non-Scan DFT Method," ats, pp.305, 11th Asian Test Symposium (ATS'02), 2002

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