Secure transmission over wireline/wireless net- works requires encryption of data and control infor- mation. For high-speed data transmission, it would be desirable to implement the encryption algorithms in hardware. Faults in the hardware, however, may cause interruption of service and side-channel attacks. This paper presents a simple technique for achieving fault tolerance in pipelined implementation of symmet- ric block ciphers. It detects errors, locates the corre- sponding faults, and readily reconfigures during nor- mal operation to isolate the identified faulty modules. Bypass links with some extra pipeline stages are used to achieve fault tolerance. The hardware overhead can be controlledby properly choosing the number of ex- tra stages. Moreover, fault tolerance is achieved with negligible time overhead.