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11th Asian Test Symposium (ATS'02)
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits
Guam, USA
November 18-November 20
ISBN: 0-7695-1825-7
Marong Phadoongsidhi, University of Wisconsin - Madison
Kim T. Le, University of Canberra
Kewal K. Saluja, University of Wisconsin - Madison
Existing principle for crosstalk fault simulation requires the storage of waveform representation at each node in the circuit throughout a time frame. At the end of each time frame a pair of waveforms, one belonging to an aggressor node, and one depicting a victim node, is inspected. If the fault is captured, it will be simulated until it is either detected or the test vectors are exhausted. This fault detection method can require a prohibitive amount of computation time for a large sequential circuit with high number of possible fault pairs to be tested. With our simulation technique introduced in this paper, these operations can be processed concurrently for many faults. The fault list dynamically adjusts itself during the simulation to accommodate fault injection and fault dropping. Experimental results on ISCAS?89 benchmark circuits show that a substantial improvement in CPU time over a conventional method is achieved with a trade-off in the amount of memory consumed.
Citation:
Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja, "A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits," ats, pp.182, 11th Asian Test Symposium (ATS'02), 2002
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