In delay fault detection BIST (Built-In-Self-Test), adjacency test pattern generation scheme can gener- ate robust test patterns effectively. Traditional adja- cency test pattern generation scheme uses LFSR to generate initial vectors, they can not handle the cir- cuit with more than 30 inputs. In this paper, a de- termined BIST scheme where several seeds are applied proposed. Based on analysis of independent partial circuits in the circuit under test, an algorithm is used generate the seeds, the small number of necessary initial vectors. Through combining outputs of shift reg- ister, the stage of shift register is reduced. Experiments show that the method of this paper has maximum fault coverage, and short test length that means short test time. The hardware overhead is in the same level with traditional methods.