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11th Asian Test Symposium (ATS'02)
A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique
Guam, USA
November 18-November 20
ISBN: 0-7695-1825-7
Toshinori Hosokawa, Semiconductor Technology Academic Research Center (STARC)
Hiroshi Date, Semiconductor Technology Academic Research Center (STARC)
Michiaki Muraoka, Semiconductor Technology Academic Research Center (STARC)
This paper proposes a state reduction method for non-scan based FSM (Finite State Machines) testing with don't care inputs identification technique. States for FSM testing are classified into valid test states and invalid test states. This method reduces the numbers of invalid test states and valid test states using a don't care input identification technique and a state compaction technique. The test length may be shortened by reducing the number of valid test states and additional test area is reduced by reducing the number of invalid test states. Experimental results for MCNC'91 FSM benchmarks and practical FSMs show that the proposed method reduces the test area by 13 to 77% and shorten the test lengths by 10 to 36%.
Citation:
Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, "A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique," ats, pp.55, 11th Asian Test Symposium (ATS'02), 2002
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