Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, we will introduce a method to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, we will introduce concrete examples where an improvement in the yield was accomplished through the use of this calculation method.