Recently we proposed a noise model to measure the dynamic noise immunity of high speed circuits. We adopt this model to verify a design for cross-talk faults. We also define a qualitative measure of delay fault immunity of a circuit. Design of a precharge-evaluate circuit was verified using this model and a number of nodes, which are susceptible to cross-talk faults were identified. Finally, we propose a new array based layout architecture namely, O²ABA (Optimized Overlaying Array Based Architecture) to improve performance predictability of a circuit through cross talk reduction. A 4-bit full adder circuit was implemented using both standard cell design and O²ABA. It is observed that circuit implemented using O²ABA is significantly less sensitive to delay faults than its standard cell design counterpart.