loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
10th Asian Test Symposium (ATS'01)
A Unified Scheme for Designing Testable State Machines
Kyoto, Japan
November 19-November 21
ISBN: 0-7695-1378-6
ASCII Text
x 
 
P. K. Lala, A. Walker, "A Unified Scheme for Designing Testable State Machines," Asian Test Symposium, pp. 273, 10th Asian Test Symposium (ATS'01), 2001.
 
 
BibTex
x
 
@article{ 10.1109/ATS.2001.990295,
author = {P. K. Lala and A. Walker},
title = {A Unified Scheme for Designing Testable State Machines},
journal ={Asian Test Symposium},
volume = {0},
year = {2001},
isbn = {0-7695-1378-6},
pages = {273},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2001.990295},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - A Unified Scheme for Designing Testable State Machines
SN - 0-7695-1378-6
SP
EP
A1 - P. K. Lala,
A1 - A. Walker,
PY - 2001
VL - 0
JA - Asian Test Symposium
ER -
 
P. K. Lala, University of Arkansas
A. Walker, North Carolina A&T State University
An approach for designing state machines that have built-in on-line and off-line testability is proposed. The next state logic is designed using transmission gates and tri-state buffers only. The resulting machines have scan_in/scan_out capability that allows off-line testing of the next state logic. The on-line testing capability for erroneous state transitions is achieved by EX-ORing the outputs of two registers that store the current and the next state of a machine, and checking for even parity at the outputs of the EX-OR gates.
Citation:
P. K. Lala, A. Walker, "A Unified Scheme for Designing Testable State Machines," ats, pp.273, 10th Asian Test Symposium (ATS'01), 2001
Usage of this product signifies your acceptance of the Terms of Use.