A practical EB-testing-pad method, that enables higher observability of multi-level wiring LSIs without any increase of chip size, has been evaluated by using actual O.25-um SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), one with and one without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 4%. It was also found that capacitances from neighboring wires will increase only by at most 2% due to the testing pads. Thus, the testing pad method has been proved to be sufficiently practical as a design method suitable for failure analysis.