IDDQ Sensing Technique for High Speed IDDQ Testing

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Teppei Takeda Articles by Masaki Hashizume Articles by Masahiro Ichimiya Articles by Hiroyuki Yotsuyanagi Articles by Yukiya Miura Articles by Kozo Kinoshita

10th Asian Test Symposium (ATS'01)

Kyoto, Japan

November 19-November 21

ISBN: 0-7695-1378-6

	ASCII Text	x
	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita, "IDDQ Sensing Technique for High Speed IDDQ Testing," Asian Test Symposium, pp. 111, 10th Asian Test Symposium (ATS'01), 2001.

	BibTex	x
	@article{ 10.1109/ATS.2001.990268, author = {Teppei Takeda and Masaki Hashizume and Masahiro Ichimiya and Hiroyuki Yotsuyanagi and Yukiya Miura and Kozo Kinoshita}, title = {IDDQ Sensing Technique for High Speed IDDQ Testing}, journal ={Asian Test Symposium}, volume = {0}, year = {2001}, isbn = {0-7695-1378-6}, pages = {111}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2001.990268}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - IDDQ Sensing Technique for High Speed IDDQ Testing SN - 0-7695-1378-6 SP EP A1 - Teppei Takeda, A1 - Masaki Hashizume, A1 - Masahiro Ichimiya, A1 - Hiroyuki Yotsuyanagi, A1 - Yukiya Miura, A1 - Kozo Kinoshita, PY - 2001 VL - 0 JA - Asian Test Symposium ER -

Teppei Takeda, The University of Tokushima

Masaki Hashizume, The University of Tokushima

Masahiro Ichimiya, The University of Tokushima

Hiroyuki Yotsuyanagi, The University of Tokushima

Yukiya Miura, Tokyo Metropolitan University

Kozo Kinoshita, Osaka Gakuin University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2001.990268

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_DDQ sensor design and external I_DDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.

Citation:

Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita, "IDDQ Sensing Technique for High Speed IDDQ Testing," ats, pp.111, 10th Asian Test Symposium (ATS'01), 2001

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.