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10th Asian Test Symposium (ATS'01)
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States
Kyoto, Japan
November 19-November 21
ISBN: 0-7695-1378-6
Hiroyuki Yotsuyanagi, University of Tokushima
Shinsuke Hata, University of Tokushima
Masaki Hashizume, University of Tokushima
Takeomi Tamesada, University of Tokushima
In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly unreachable states. Experimental results for ISCAS benchmark circuits are shown.
Citation:
Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada, "Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States," ats, pp.23, 10th Asian Test Symposium (ATS'01), 2001
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