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10th Asian Test Symposium (ATS'01)
Design for Hierarchical Two-Pattern Testability of Data Paths
Kyoto, Japan
November 19-November 21
ISBN: 0-7695-1378-6
Md. Altaf-Ul-Amin, Nara Institute of Science and Technology
Satoshi Ohtake, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
This paper introduces the concept of hierarchical testability of data paths for delay faults. A definition of hierarchically two-pattern testable (HTPT) data path is developed. Also, a design for testability (DFT) method is presented to augment a data path to an HTPT one. The DFT method incorporates a graph-based analysis of an HTPT data path and makes use of some graph algorithms. The proposed method can provide the similar advantages of the enhanced scan approach at the cost of much lower hardware overhead.
Citation:
Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara, "Design for Hierarchical Two-Pattern Testability of Data Paths," ats, pp.11, 10th Asian Test Symposium (ATS'01), 2001
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