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Ninth Asian Test Symposium (ATS'00)
Testing domino circuits in SOI technology
Taipei, Taiwan
December 04-December 06
ISBN: 0-7695-0887-1
ASCII Text
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E. MacDonald, N.A. Touba, "Testing domino circuits in SOI technology," Asian Test Symposium, pp. 441, Ninth Asian Test Symposium (ATS'00), 2000.
 
 
BibTex
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@article{ 10.1109/ATS.2000.893664,
author = {E. MacDonald and N.A. Touba},
title = {Testing domino circuits in SOI technology},
journal ={Asian Test Symposium},
volume = {0},
year = {2000},
issn = {1081-7735},
pages = {441},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893664},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asian Test Symposium
TI - Testing domino circuits in SOI technology
SN - 1081-7735
SP
EP
A1 - E. MacDonald,
A1 - N.A. Touba,
PY - 2000
KW - CMOS logic circuits; silicon-on-insulator; fault simulation; leakage currents; logic testing; automatic testing; integrated circuit testing; domino circuits; SOI technology; dynamic circuit styles; fault modeling analysis; overall fault coverage; parasitic bipolar leakage; CMOS logic
VL - 0
JA - Asian Test Symposium
ER -
 
E. MacDonald, Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
N.A. Touba, Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
The proliferation of both partially depleted silicon-on-insulator (PDSOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino circuits fabricated in SOI technology and new tests are proposed to address the interactions. A fault modeling analysis is described which demonstrates that the overall fault coverage can be improved beyond that of traditional testing of domino circuits in bulk technology.
Index Terms:
CMOS logic circuits; silicon-on-insulator; fault simulation; leakage currents; logic testing; automatic testing; integrated circuit testing; domino circuits; SOI technology; dynamic circuit styles; fault modeling analysis; overall fault coverage; parasitic bipolar leakage; CMOS logic
Citation:
E. MacDonald, N.A. Touba, "Testing domino circuits in SOI technology," ats, pp.441, Ninth Asian Test Symposium (ATS'00), 2000
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