Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

A
ATS
2000
Ninth Asian Test Symposium (ATS'00)
Abstract - Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

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	Similar Articles Articles by M.L. Flottes Articles by C. Landrault Articles by A. Petitqueux

Ninth Asian Test Symposium (ATS'00)

Taipei, Taiwan

December 04-December 06

ISBN: 0-7695-0887-1

	ASCII Text	x
	M.L. Flottes, C. Landrault, A. Petitqueux, "Design for sequential testability: an internal state reseeding approach for 100 % fault coverage," Asian Test Symposium, pp. 404, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893657, author = {M.L. Flottes and C. Landrault and A. Petitqueux}, title = {Design for sequential testability: an internal state reseeding approach for 100 % fault coverage}, journal ={Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {404}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893657}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Design for sequential testability: an internal state reseeding approach for 100 % fault coverage SN - 1081-7735 SP EP A1 - M.L. Flottes, A1 - C. Landrault, A1 - A. Petitqueux, PY - 2000 KW - sequential circuits; logic design; logic testing; design for testability; fault diagnosis; controllability; automatic test pattern generation; observability; sequential testability; internal state reseeding; fault coverage; observation points; flip-flops; partial reset; minimum DFT insertion; non-scan approach; at-speed testing; controllability; benchmark circuits; fault efficiency; ATPG; CPU time; 100 percent VL - 0 JA - Asian Test Symposium ER -

M.L. Flottes, Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France

C. Landrault, Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France

A. Petitqueux, Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893657

This paper proposes a method to select observation points and flip-flops for partial reset. The method does not target minimum DFT insertion but a maximum improvement on testability. The proposed non-scan approach allows a at-speed testing. Experimental results show that the method achieves 100% fault coverage and 100% fault efficiency for benchmark circuits while requiring less ATPG effort (CPU time) with no scan necessity.

Index Terms:

sequential circuits; logic design; logic testing; design for testability; fault diagnosis; controllability; automatic test pattern generation; observability; sequential testability; internal state reseeding; fault coverage; observation points; flip-flops; partial reset; minimum DFT insertion; non-scan approach; at-speed testing; controllability; benchmark circuits; fault efficiency; ATPG; CPU time; 100 percent

Citation:

M.L. Flottes, C. Landrault, A. Petitqueux, "Design for sequential testability: an internal state reseeding approach for 100 % fault coverage," ats, pp.404, Ninth Asian Test Symposium (ATS'00), 2000

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